1. Field of the Invention
The present invention is directed to a binary comparator, and in particular to a simply-constituted binary comparator capable of comparing two binary digits in a short time.
In the present specification, binary digits A and B (`A=a.sub.n a.sub.n-1 . . . a.sub.0 `, `B=b.sub.n b.sub.n-1 . . . b.sub.0 `) are compared in the case that the number of bits is 4, that is, n is 3, as an example.
2. Description of the Background Art
FIG. 1 is a constitutional diagram of a binary comparator implemented with full adders in accordance with the conventional art. The conventional binary comparator includes: four inverters (INV3, INV2, INV1, INV0) for respectively inverting the logic states of each bit (b3, b2, b1, b0) of a binary digit B; full adders (ADD3, ADD2, ADD1, ADD0) to which the outputs of the inverters (INV3, INV2, INV1, INV0) and each bit of a binary digit A (a3, a2, a0, a1) are respectively inputted; inverters (INV13, INV12, INV11, INV10) for respectively inverting the outputs of the full adders (ADD3, ADD2, ADD1, ADD0); and an AND gate (AND10) for ANDing the outputs of the inverters (INV13, INV12, INVL11, INV10). The carry input of the full adder (ADD0) at the LSB location is always set to 1, and the carry is externally outputted from the full adder (ADD3) at the MSB location.
The operation of the above-mentioned binary comparator implemented with full adders in accordance with the conventional art will now be described. In order to explain the operation thereof easily, it is assumed that the binary digit A is 1011.sub.2 and the binary digit B is 1001.sub.2. Therefore, a3=1, a2=0, a1=1, a0=1 and b3=1, b2=0, b1=0, b0=1.
The bit `a0=1`, the bit `bo=0` and the carry `1` are inputted to the full adder (ADD0). As a result, the sum and the carry values respectively become `0` and `1`. The sum `0` becomes `1` after being inverted in the inverter (INV10).
The bit `a1=1` and the bit `b1=1` are inputted to the full adder (ADD1), and the carry `1` is inputted from the full adder (ADD0) to the full adder (ADD1). Consequently, both the sum and the carry values become `1`. The sum `1` becomes `0` after being inverted in the inverter (IVN11).
The bit `a2=0` and the bit `b2=1` are inputted to the full adder (ADD2), and the carry `1` is inputted from the full adder (ADD1) to the full adder (ADD2). Accordingly, the sum and the carry values respectively become `0` and `1`. The sum `0` becomes `1` after being inverted in the inverter (INV12).
The bit `a3=1` and the bit `b3=0` are inputted to the full adder (ADD3), and the carry `1` is inputted from the full adder (ADD2) to the full adder (ADD3). As a result, the sum and the carry values respectively become `0` and `1`. The sum `0` becomes `1` after being inverted in the inverter (INV13). Here, the carry `1` is outputted externally. The carry `1` implies that the binary digit A is larger than the binary digit B.
The respective outputs `1`, `1`, `0` and `1` of the inverters (INV13, INV12, INV11, INV10) are ANDed in the AND gate (AND 10). Consequently, the output thereof becomes `0`, which implies that the binary digits A and B are not equal.
As described above, the respective full adders in conjunction with the input inverters perform A-B operation, namely, a subtraction. In the case that the outputs of all full adders are `0`, then A is equal to B. However, in the case the output of the carry is `1`, then A is larger than B.
The operations performed above are represented by the following logic expressions. EQU (A=B).tbd.(a3.sym.b3).multidot.(a2.sym.b2).multidot.(a1.sym.b1).multidot.(a 0.sym.b0) (1) EQU (A&gt;B).tbd.a3b3+a2b2(a3.sym.b3)+a1b1(a3.sym.b3)(a2.sym.b2)+a0b0(a3.sym.b3)(a 2.sym.b2)(a1.sym.b1) (2)
Here, `.sym.` and `(a.sub.i .sym.b.sub.i)` respectively represent an exclusive-OR operation and an exclusive-NOR operation.
Expression (1) implies that A is equal to B if the values of the respective bits are equal to each other. Expression (2) implies that the values of the bits a3 and b3 which are respectively MSB[s] of the binary digits A and B are compared, and then, if the values thereof (a3, b3) are equal to each other, the value of the bit a2 is compared with that of the bit b2, and if the values thereof (a2, b2) are equal, the value of the bit a1 is compared with that of the bit b1, and then, if the values thereof (a1, b1) are equal, the value of the bit a0 is compared with the value of the bit b0.
The entire operation speed of the circuit is determined by the full adder thereof. However, the above four full adders are complex in constitution because they include multiple transistors.
FIG. 2 is a constitutional diagram of a binary comparator implemented with logic gates in accordance with the conventional art. The constitution of the binary comparator in FIG. 2 is simpler than that of the binary comparator in FIG. 1 because the binary comparator illustrated in FIG. 2 is constituted by using the boolean properties represented in Expressions (1) and (2).
As shown in FIG. 2, the binary comparator includes four NOR gates (NOR3, NOR2, NOR1, NOR0), four AND gates (AND23, AND22, AND21, AND20), and an OR gate (OR).
The Nor gate (NOR3) performs the exclusive-NOR operation `(a.sub.3 .sym.b.sub.3)` upon the input bits (a.sub.3, b.sub.3) and the other NOR gates (NOR2-NOR0) also perform exclusive-NOR operations upon the input bits (a.sub.2, b.sub.2) (a.sub.1, b.sub.1) (a.sub.0, b.sub.0), respectively.
The respective outputs of the four NOR gates (NOR3-NOR0) are ANDed in the AND gate (AND20). The operation performed in the AND gate (AND 20) is represented in the above logic expression (1).
That is, the AND gates (AND23, AND22, AND21) respectively perform the operations `a.sub.2 b.sub.2 (a.sub.3 .sym.b.sub.3)`, `a.sub.1 b.sub.1 (a.sub.3 .sym.b.sub.3)(a.sub.2 .sym.b.sub.2)` and `a.sub.0 b.sub.0 (a.sub.3 .sym.b.sub.3)(a.sub.2 .sym.b.sub.2)(a.sub.1 .sym.b.sub.1)`. In addition, the operation performed in the OR gate (OR) is represented by the above logic expression (2).
However, the constitution of the binary comparator adopting the logic gates in accordance with the conventional art illustrated in FIG. 2 is also complex due to the multiple transistors. Accordingly, the binary comparators described above have a disadvantage in that the operation speed thereof is slow.